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HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM Document Title
4Bank x 512K x 32bits Synchronous DRAM
Revision History
Revision No. 0.1 0.2 0.3 Initial Draft Removed Preliminary
1. Updated Output Load Capacitance for Access Time Measurement CL = 30pF in AC OPERATING TEST CONDITION 2. Updated the tolerance zone of the leads and the description of the package type in PACKAGE DIMENSION
History
Draft Date May. 2004 July 2004 Sep. 2004
Remark Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Sep. 2004 1
HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM
DESCRIPTION
The Hynix HY57V643220D(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V643220D(L/S)T(P) is organized as 4banks of 524,228x32. HY57V643220D(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)
FEATURES
* * * * * * Voltage : VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface JEDEC standard 400mil 86pin TSOP-II with 0.5mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM 0, 1, 2 and DQM 3 Internal four banks operation * * * * * Auto refresh and self refresh 4096 Refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks Burst Read Single Write operation
ORDERING INFORMATION
Part No. HY57V643220D(L/S)T(P)-45 HY57V643220D(L/S)T(P)-5 HY57V643220D(L/S)T(P)-55 HY57V643220D(L/S)T(P)-6 HY57V643220D(L/S)T(P)-7
Note 1. HY57V643220DT(P) 2. HY57V643220DLT(P) 3. HY57V643220DST(P) 4. HY57V643220D(L/S)T 5. HY57V643220D(L/S)TP
Clock Frequency 222MHz 200MHz 183MHz 166MHz 143MHz
Organization
Interface
Package
4Banks x 512Kbits x32
LVTTL
86pin TSOP-II (Lead Free)
Series : Normal Power Series : Low Power Series : Super Low Power Series : Leaded Series : Lead Free
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Sep. 2004 2
HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM 86PIN TSOP II CONFIGURATION
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD
1 2 3
86 85 84
20 21 22
86Pin TSOP II 400Mil x 875mil 0.5mm Pin Pitch
67 66 65
41 42 43
46 45 44
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
Rev. 0.3 / Sep. 2004
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HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM
Pin FUNCTION DESCRIPTIONS
Pin CLK CKE CS BA0, BA1 A0 ~ A10 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/ Ground No Connection Pin Name DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
RAS, CAS, WE
DQM0~3 DQ0 ~ DQ31 VDD/VSS VDDQ/VSSQ NC
Rev. 0.3 / Sep. 2004
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HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM FUNCTIONAL BLOCK DIAGRAM
512Kbit x 4banks x 32 I/O Low Power Synchronous DRAM
Self refresh logic & timer
Internal Row Counter
CLK CKE
State Machine Row Active
512Kx32 BANK 3
Row Pre Decoder
512Kx32 BANK 2 512Kx32 BANK 1 512Kx32 BANK 0
DQ0
I/O Buffer & Logic Sense AMP & I/O Gate
X-Decoder X-Decoder X-Decoder X-Decoder
CS RAS CAS
Refresh
Memory Cell Array
Column Active
WE DQM0~3
Column Pre Decoder
DQ31
Y-Decoder
Bank Select
Column Add Counter
A0 A1
Address Buffers
Address Register
Burst Counter
A10
BA1 BA0
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.3 / Sep. 2004
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HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1 0 BA0 0 A11 0 A10 0 A9 OP Code A8 0 A7 0 A6 A5 CAS Latency A4 A3 BT A2 A1 Burst Length A0
OP Code
A9 0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write
Burst Type
A3 0 1 Burst Type Sequential Interleave
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved
Burst Length
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length A3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page A3=1 1 2 4 8 Reserved Reserved Reserved Reserved
Rev. 0.3 / Sep. 2004
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HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM ABSOLUTE MAXIMUM RATING
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature Time
.
Symbol TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER
Rating -40 ~ 85 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 10
.
Unit
oC o
C
V V V mA W
oC . Sec
DC OPERATING CONDITION (TA= -40 to 85oC )
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 3.3 Max 3.6 VDDQ+0.3 0.8 Unit V V V Note 1 1, 2 1, 3
Note : 1. All voltages are referenced to VSS = 0V 2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration
AC OPERATING TEST CONDITION (TA= -40 to 85 oC, VDD=3.30.3V, VSS=0V)
Parameter AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 30 Unit V V ns V pF Note
CAPACITANCE (TA= -40 to 85 oC, f=1MHz, VDD=3.3V)
Parameter CLK Input capacitance Data input / output capacitance A0 ~ A10, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM 0~3 DQ0 ~ DQ31 Pin Symbol CI1 CI2 CI/O Min 2.5 2.5 4 Max 3.5 3.8 6.5 Unit pF pF pF
Rev. 0.3 / Sep. 2004
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HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM
Note 1.
Vtt=1.4V
Vtt=1.4V
RT=500
RT=50
Output 30pF
Output
Z0 = 50
30pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERRISTICS I (TA= 0 to 70oC)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
Note : 1. VIN = 0 to 3.6V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6
Symbol ILI ILO VOH VOL
Min -1 -1 2.4 -
Max 1 1 0.4
Unit uA uA V V
Note 1 2
IOH = -2mA IOL = +2mA
Rev. 0.3 / Sep. 2004
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HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM DC CHARACTERISTICS II (TA= 0 to 70oC)
Parameter Symbol IDD1 Test Condition Burst length=1, One bank active tRC tRC(min), IOL=0mA Speed 45 220 5 200 55 190 2 2 6 180 7 170 Unit Note
Operating Current
mA mA mA
1
Precharge Standby Cur- IDD2P CKE VIL(max), tCK = 15ns rent IDD2PS CKE VIL(max), tCK = in Power Down Mode CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable.
Precharge Standby Cur- IDD2N rent in Non Power Down Mode IDD2NS
17 mA 12 3 3
Active Standby Current IDD3P CKE VIL(max), tCK = 15ns in Power Down Mode IDD3PS CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active CL=3 290 260 280 250
mA
Active Standby Current IDD3N in Non Power Down Mode IDD3NS Burst Mode Operating Current Auto Refresh Current IDD4 IDD5
40 mA 30 260 235 2 0.8 450 240 220 210 210 mA mA mA mA uA 1 2 3 4 5
tRC tRC(min), All banks active
Normal
Self Refresh Current
IDD6
CKE 0.2V
Low Power Super Low Power
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. HY57V643220DT(P) Series 4. HY57V643220DLT(P) Series 5. HY57V643220DST(P) Series
Rev. 0.3 / Sep. 2004
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HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter CAS Latency=3 CAS Latency=2 Symbol tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 45 5 55 6 7 Unit Note ns 1000 10 5.5 6.0 5.5 6.0 3.0 3.0 2.0 1.75 1.0 1.75 1.0 1.75 1.0 1.75 1.0 1.0 5.5 6.0 5.5 6.0 ns ns ns ns 2 1.5 1.3 0.8 1.3 0.8 1.3 0.8 1.3 0.8 1.0 6.0 4.0 6.0 1.5 1.5 1.0 1.5 1.0 1.5 1.0 1.5 1.0 1.0 6.0 4.5 6.0 2.0 1.5 1.0 1.5 1.0 1.5 1.0 1.5 1.0 1.0 6.0 5.0 6.0 2.0 1.5 1.0 1.5 1.0 1.5 1.0 1.5 1.0 1.0 ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1
Min Max Min Max Min Max Min Max Min Max 4.5 1000 10 1.75 1.75 4.5 10 2.0 2.0 4.5 5.0 1000 10 2.25 2.25 5.0 5.5 1000 10 2.5 2.5 6.0 1000 7.0
System Clock Cycle Time
Clock High Pulse Width Clock Low Pulse Width Access Time From Clock CAS Latency=3 CAS Latency=2
Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time CAS CLK to Latency=3 Data Output in High-Z Time CAS Latency=2
Note :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 2.0V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
Rev. 0.3 / Sep. 2004
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HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter RAS Cycle Time RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z CAS Latency=3 CAS Latency=2 Operation Auto Refresh 45 5 55 6 7 SymUnit Note bol Min Max Min Max Min Max Min Max Min Max tRC tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tDPE tSRE tREF 2 0 2 3 1 1 64 2 0 2 3 2 1 1 64 58.5 58.5 18 55 55 15 55 55 16.5 60 60 18 42 18 12 1 0 1 100K 63 63 20 42 20 14 1 0 1 100K ns ns ns ns ns ns CLK CLK CLK
40.5 100K 38.7 100K 38.7 100K 18 9 1 0 TBD 15 10 1 0 TBD 16.5 11 1 0 TBD -
tDPL + tRP 2 0 2 3 2 1 1 64 2 0 2 3 2 1 1 64 2 0 2 3 2 1 1 64 CLK CLK CLK CLK CLK CLK CLK ms 1
Power Down Exit Time Self Refresh Exit Time Refresh Time
Note : 1. A new command can be given tRC after self refresh exit.
Rev. 0.3 / Sep. 2004
11
HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM
COMMAND TRUTH TABLE
Command Mode Register Set No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop DQM Auto Refresh Burst-Read-Single-WRITE Entry Self Refresh1 Exit CKEn-1 H H H H CKEn X X X X CS L H L L L RAS L X H L H CAS L X H H L WE L X H H H DQM X X X X CA RA L H L H H L X X X A9 ball High (Other balls OP code) MRS
Mode
ADDR
A10/AP OP code X
BA
Note
V V
H
X
L
H
L
L
X
CA
V X V
H H H H H H L
X X
L L
L H X
H H
L L
X X V
X
H X L H
L L L H L H L H L H L
L L L X H X H X H X V X
L L L X H X H X H X V
H L H X H X H X H X V
X X X X
X
Entry Precharge power down Exit
H
L
X X X
L
H
Clock Suspend
Entry Exit
H L
L H
X X
X
Rev. 0.3 / Sep. 2004
12
HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM PACKAGE INFORMATION
JEDEC STANDARD 400mil 86pin TSOP-II with 0.5mm pin pitch
Unit : mm(inch)
22.327(0.8790) 22.149(0.8720)
11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960)
0.150(0.0059) 0.050(0.0020)
1.194(0.0470) 0.991(0.0390)
0.50(0.0197)
0.21(0.008) 0.18(0.007)
5deg 0deg
0.597(0.0235) 0.210(0.0083) 0.406(0.0160) 0.120(0.0047)
0.05
0.05 M
Rev. 0.3 / Sep. 2004
13

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